Conventional architecture for computer systems using devices such as microprocessors and digital signal processors (DSP) utilize instruction code supplied to these devices containing interrupt requests. Such an interrupt request instructs the central processing unit of the device to perform a routine or subroutine to service an external hardware device, such as a printer, modem, input device, etc. In many computer systems, a large number of such hardware devices are to be serviced. In such cases, the interrupt request for each of the devices may be assigned a different priority level to assure that the interrupt request of certain of the devices have priority over others and will be serviced first. Conflicts are possible relative to the action to be taken to service a plurality of the interrupt requests that occur or are pending at the same time. Therefore, there is a need to arbitrate the possible conflicts to assure proper operation of the central processing unit relative to servicing of the interrupt requests in a predetermined priority order.
The present invention is directed to a circuit operable in conjunction with a computer or DSP that supports multiple hardware interrupt requests having multiple levels of user-assigned priorities. There are two reasons for assigning priorities to the interrupts. The first is to permit nesting of interrupts, i.e., an interrupt service routine being performed can be interrupted by an interrupt of higher priority. The second is the servicing of concurrently pending interrupts according to their priority.
In the present invention, when an interrupt request occurs for one of a plurality of devices, a corresponding assigned bit is set in a register (INS) and the interrupt is then considered to be pending. Corresponding to each bit set in the INS register is an entry in a register (INC0 or INC1) corresponding to an interrupt priority level as assigned by the user by writing values into this register. In the preferred embodiment, the priority levels range from level 0 (fully disabled) to level 3 (highest level). A current interrupt priority level (CIPL), set from another part of the computer or DSP, establishes the priority level, or levels, of the pending interrupts which are to be selected for servicing. The pending interrupt is considered for selection for servicing if its programmable priority level is higher than the CIPL.
If multiple interrupts of the same priority level are pending, then only one interrupt may be serviced. The circuit of the invention arbitrates between competing interrupts as follows: 1) the interrupt with the highest priority level is the next to be serviced; 2) if multiple interrupts are pending with the same maximum priority level, then the pending interrupt with the lowest bit position in the INS register is the next to be serviced.
The interrupt specification requires the circuit to first evaluate each interrupt against its programmed priority level, and then to arbitrate competing interrupts by accounting for priority level and bit position in the INS register. The circuit completes the arbitration process within one clock cycle of the computer. In addition, the circuit encodes the interrupt into an offset field of fixed bit size for use in a following computing phase.
It is an object of the invention to provide a circuit to select an interrupt request for servicing from a plurality of requests based upon assigned priority levels for the various requests.
An additional object is to provide a circuit to first evaluate each of a plurality of pending interrupt requests of different priority levels against a programmed priority level, and that arbitrates between competing multiple pending interrupts having the same priority level by accounting for bit positions in a register of the competing interrupts.
Another object is to provide a circuit that arbitrates between competing pending interrupt requests with assigned priority levels in which the interrupt with the highest priority level is the next selected to be serviced and if multiple interrupts are pending with the same priority level, then the pending interrupt of that priority level as set in the lowest bit position of a register is the next to be serviced.